november 2013 fqt2p25 p-channel qfet ? mosfet -250 v, -0.55 a, 4.0 ? description fqt2p25 p-channel qfet ? mosfet ?2001 fairchild semiconductor corporation fqt2p25 rev. c0 www.fairchildsemi.com 1 these p-channel enhancement mode power field effect transistors are produced using fairchilds proprietary, planar stripe, dmos technology. this advanced technology has been especially tailored to minimize on- state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and c ommutation mode. these devices are well suited for high efficiency switching dc/dc converters. features absolute maximum ratings t c = 25 o c unless otherwise noted. ? -0.55 a, -250 v, r ds(on) = 4.0 ? (max.) @ v gs = -10 v, i d = -0.275 a ? low gate charge (typ. 6.5 nc) ? low crss (typ. 6.5 pf) ? 100% avalanche tested g s d sot-223 d d d s g g thermal characteristics symbol parameter FQT2P25TF unit v dss drain-source voltage -250 v i d drain current - continuous (t c = 25c) -0.55 a - continuous (t c = 100c) -0.35 a i dm drain current - pulsed (note 1) -2.2 a v gss gate-source voltage 30 v e as single pulsed avalanche energy (note 2) 120 mj i ar avalanche current (note 1) -0.55 a e ar repetitive avalanche energy (note 1) 0.25 mj dv/dt peak diode recovery dv/dt (note 3) -5.5 v/ns p d power dissipation (t c = 25c) 2.5 w - derate above 25c 0.02 w/c t j , t stg operating and storage temperature range -55 to +150 c t l maximum lead temperature for soldering purposes, 1/8 " from case for 5 seconds 300 c symbol parameter FQT2P25TF unit r ja thermal resistance, junction-to-ambient * 50 c / w * when mounted on the minimum pad size recommended (pcb mount)
package marking and ordering information part number top mark package reel size tape width quantity fqt2p25 FQT2P25TF sot-223 13 " 12 mm 4000 units fqt2p25 p-channel qfet ? mosfet ?2001 fairchild semiconductor corporation fqt2p25 rev. c0 www.fairchildsemi.com 2 1. repetitive rating: pulse- width limited by maximum junction temperature. 2. l = 635 mh, i as = - 0.55 a, v dd = -50 v, r g = 25 ? , starting t j = 25 o c. 3. i sd - 2.3 a, di/dt 300 a/s, v dd b v dss , starting t j = 25 o c. 4. essentially independent of operating temperature. packing method tape and reel electrical characteristics t c = 25 o c unless otherwise noted. ( n ote 4) ( note 4) symbol parameter test conditions min typ max unit off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = -250 a -250 -- -- v b vdss / t j breakdown voltage temperature coefficient i d = -250 a, referenced to 25c -- -0.2 -- v/c i dss zero gate voltage drain current v ds = -250 v, v gs = 0 v -- -- -1 a v ds = -200 v, t c = 125c -- -- -10 a i gssf gate-body leakage current, forward v gs = -30 v, v ds = 0 v -- -- -100 na i gssr gate-body leakage current, reverse v gs = 30 v, v ds = 0 v -- -- 100 na on characteristics v gs(th) gate threshold voltage v ds = v gs , i d = -250 a -3.0 -- -5.0 v r ds(on) static drain-source on-resistance v gs = -10 v, i d = -0.275 a -- 3.15 4.0 g fs forward transconductance v ds = -40 v, i d = -0.275 a -- 0.6 -- s dynamic characteristics c iss input capacitance v ds = -25 v, v gs = 0 v, f = 1.0 mhz -- 190 250 pf c oss output capacitance -- 40 55 pf c rss reverse transfer capacitance -- 6.5 8.5 pf switching characteristics t d(on) turn-on delay time v dd = -125 v, i d = -2.3 a, r g = 25 -- 8.5 25 ns t r turn-on rise time -- 40 90 ns t d(off) turn-off delay time -- 12 35 ns t f turn-off fall time -- 25 60 ns q g total gate charge v ds = -200 v, i d = -2.3 a, v gs = -10 v -- 6.5 8.5 nc q gs gate-source charge -- 1.8 -- nc q gd gate-drain charge -- 3.0 -- nc drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -- -- -0.55 a i sm maximum pulsed drain-source diode forward current -- -- -2.2 a v sd drain-source diode forward voltage v gs = 0 v, i s = -0.55 a -- -- -5.0 v trr reverse recovery time v gs = 0 v, i s = -2.3 a, di f / dt = 100 a/ s -- 110 -- ns qrr reverse recovery charge -- 0.4 -- c
fqt2p25 p-channel qfet ? mosfet ?2001 fairchild semiconductor corporation fqt2p25 rev. c0 www.fairchildsemi.com 3 ! 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 10 -1 10 0 25 150 notes : 1. v gs = 0v 2. 250 s pulse test -i dr , reverse drain current [a] -v sd , source-drain voltage [v] 2 68 4 1 0 10 -1 10 0 notes : 1. v ds = -40v 2. 250 s pulse test -55 150 25 -i d , drain current [a] 4 -v gs , gate-source voltage [v] 1 0 2 4 5 33 7 6 0 2 4 6 8 10 12 v ds = -125v v ds = -50v v ds = -200v note : i d = -2.3 a v gs , gate-source voltage [v] q g , total gate charge [nc] 10 -1 0 10 1 0 100 200 300 400 c iss = c gs + c gd (c ds = shorted) = c gd ds c oss = c + c gd c rss notes : 1. v gs = 0 v 2. f = 1 mhz c rss c oss c iss capacitance [pf] 10 -v ds , drain-source voltage [v] 0.0 1.5 3.0 4.5 6.0 0 3 6 9 12 15 note : t j = 25 v gs = - 20v v gs = - 10v r ds(on) [ ], drain-source on-resistance -i d , drain current [a] 10 -1 0 10 1 10 -1 10 0 v gs top : -15.0 v -10.0 v -8.0 v -7.0 v -6.5 v -6.0 v bottom : -5.5 v notes : 1. 250 s pulse test 2. t c = 25 -i d , drain current [a] 10 -v ds , drain-source voltage [v] figure 5. capacitance characteristics figure 6. gate charge characteristics figure 3. on-resistance variation vs. drain current and gate voltage figure 4. body diode forward voltage variation vs. source current and temperature figure 2. transfer characteristics figure 1. on-region characteristics
z j a (t), thermal response [ o c/w] fqt2p25 p-channel qfet ? mosfet ?2001 fairchild semiconductor corporation fqt2p25 rev. c0 www.fairchildsemi.com 4 !
25 50 75 100 125 150 0.0 0.1 0.2 0.3 0.4 0.5 0.6 -i d , drain current [a] t c , case temperature [ ] 10 -1 10 0 10 1 10 2 10 -3 10 -2 10 -1 10 0 10 1 100 ms dc 10 ms 1 ms 100 s operation in this area is limited by r ds(on) notes : 1. t c = 25 o c 2. t j = 150 o c 3. single pulse -i d , drain current [a] 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 10 2 10 3 10 -1 10 0 10 1 notes : 1. z (t) = 50 w / m a x. 2. d u ja ty d f ac to r, = t 1 /t 2 3. t jm - * t a = p dm z ja (t) s in gle pu ls e =d 0.5 0.02 0.2 0.05 0.1 0.01 -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 notes : 1. v gs = -10 v 2. i d = -0.275 a r ds(on) , (normalized) drain-source on-resistance t j , junction temperature [ o c] -100 -50 0 50 100 150 200 0.8 0.9 1.0 1.1 1.2 notes : 1. v gs = 0 v 2. i d = -250 a -bv dss , (normalized) drain-source breakdown voltage t j , junction temperature [ o c] -v ds , drain-source voltage [v] figure 9. maximum safe operating area figure 10. maximum drain current vs. case temperature figure 7. breakdown voltage variation vs. temperature figure 8. on-resistance variation vs. temperature t 1 , square w ave pulse duration [sec] figure 11. transient thermal response curve t 1 p dm t 2
figure 12. gate charge test circuit & waveform f igure 13. resistive switc hing test circuit & waveforms figure 14. unclamped inductive switching test circuit & waveforms ?2001 fairchild semiconductor corporation fqt2p25 rev. c0 www.fairchildsemi.com 5 fqt2p25 p-channel qfet ? mosfet vv dsds vv gsgs 1010%% 90%90% tt d(d(onon)) tt rr tt onon tt ofofff tt d(d(ofofff)) tt ff vv dddd vv dsds rr ll dutdut rr gg vv gsgs chchargargee vv gsgs qq gg qq gsgs qq gdgd vv gsgs dudutt vv dsds 300300nfnf 50k50k ? 200n200nff 12v12v samsamee t tyypepe as duas dutt e ee as as as === --- - 2 1 2 1 2 1 2 1 --------- --- lll asasas iii bvbv dsdsss 222 --- --- ---- ---- ---- ---- ---- ---- ----- ----- bv bv dsdsss -v-v dddd vv dddd vv dsds bvbv dssdss t t pp vv dddd ii asas vv ds ds (t)(t) ii d d (t(t)) titimmee dudutt rr gg lll iii ddd t t pp i g = const. vv gsgs vv gsgs
f igure 15. pe ak diode recovery dv/dt test circuit & waveforms fqt2p25 p-channel qfet ? mosfet ?2001 fairchild semiconductor corporation fqt2p25 rev. c0 www.fairchildsemi.com 6 ?? dutdut vv dsds ++ __ drivdriverer rr gg comcompplliimmentent of of dutdut (n-(n-cchannelhannel)) vv gsgs ?? ddvv//dtdt ccoontntrroolllleed bd byy r r gg ii sdsd ccononttrrolollleded by by pu pullsse pee perriiodod vv dddd lll ii sdsd 1010vv vv gsgs ( driv( driver )er ) ii sdsd ( dut )( dut ) vv dsds ( dut )( dut ) vv dddd bobodydy d diiooddee forforwward vard vololttagage dre dropop ii fmfm ,, bo bodydy d diiodode fe fororwwaarrd cd cuurrrrenentt vv sdsd bobodydy d diiodode re reevveerrssee c cuurrrrenentt ii rmrm bobodydy di diodode e rreecovcoveerryy dvdv/d/dtt didi//dtdt d =d = d = ---- -- gategate gate ------------------ --------- p p p ulul ul ss s ---------------- -------- e e e ww w ii i dd d ---------- ----- tt t hh h gaga ga te pute pu te pu ll l ss s ee e pepe pe rr r ii i odod od -- - -- -
?2001 fairchild semiconductor corporation fqt2p25 rev. c0 www.fairchildsemi.com 7 fqt2p25 p-channel qfet ? mosfet mechanical dimensions figure 16. sot-223, molded, 4-lead package drawings are provided as a service to customers considering fairchild com ponents. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specif- ically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packag ing area for the most recent package drawings: http://www.fairchildsemi.com/package/packagedetails.html?id=pn_tte23-004
?2001 fairchild semiconductor corporation fqt2p25 rev. c0 www.fairchildsemi.com 8 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or desi gn. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchilds worldwide terms and conditio ns, specifically the warranty therein, which covers these products. life support policy fairchilds products are not authorized for use as critical components in life support de vices or systems without the express written approval of fai rchild semiconductor corporation. as used here in: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms accupower? 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fqt2p25 p-channel qfet ? mosfet
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